← Back to Insights
Industry Analysis4 min read

The Semiconductor Reset: An Industrial-Policy Scorecard, Four Years On

By Hannah Park, Head of Technology Sector Research

Four years on from the wave of industrial-policy programmes that committed close to half a trillion dollars to reshaping the global semiconductor supply chain — the US CHIPS and Science Act, the EU Chips Act, Japan's Rapidus-anchored framework, and Korea's K-Chips support — the strategic question has shifted decisively. It is no longer "Will Western governments build leading-edge capacity?" The answer to that is yes; capacity is being built, and the timelines are credible. The question is whether the new geography of advanced semiconductors is competitive at price points the market will bear, and what that means for the corporate buyers who depend on it.

The honest 2026 answer: capacity policy is working. Cost policy is not.

What the Capital Has Actually Built

Three industrial outcomes are now visible and defensible:

Leading-edge capacity outside Taiwan and Korea exists for the first time in a generation. TSMC's Arizona fabs are producing N4 in volume, with N3 ramping through 2026 and N2 committed for the late-decade window. Samsung's Texas operations have moved from delay narrative to production milestone. Intel's Ohio site, while behind its original schedule, is now a credible 2027–28 production anchor rather than a speculative announcement. Combined US leading-edge capacity by 2028 will exceed every published 2022 forecast.

Memory has localised more than logic. Micron's New York and Idaho expansions, SK Hynix's Indiana announcement, and Kioxia/Western Digital's investment cycle have produced a memory-supply geography that is materially less concentrated than 2022. This is the under-celebrated win of the industrial policy cycle.

Equipment and materials supply chains have repositioned. ASML, Applied Materials, Tokyo Electron, and Lam have built parallel servicing capabilities across the new fab geography. Specialty gases and chemicals — historically a single-country concentration risk — now have second-source options across multiple regions.

What the Capital Has Not Solved

Three uncomfortable cost realities are now established:

Western leading-edge wafers cost meaningfully more. The per-wafer cost premium for US-fabricated N3 versus Taiwan-fabricated N3 has stabilised in the 25–35% range. Subsidies underwrite the capex; they do not address ongoing operating costs. Without sustained tax-credit and procurement support, the Western premium is structural.

Talent constraints are the binding bottleneck. The 2024–25 hiring intensity exhausted the qualified labour pool faster than universities have replaced it. Semiconductor engineering compensation has approximately doubled in the US since 2021. The implicit subsidy from talent re-pricing is borne by the rest of the industrial economy.

Tooling export controls have second-order effects no one priced in. Restrictions on advanced equipment exports to China have pulled forward Chinese capacity in mature-node logic and memory by an estimated 18–24 months. The mature-node Chinese capacity overhang now visible in 2026 is materially larger than 2022 baselines projected, and is exerting pricing pressure on the global mature-node market.

The Strategic Map for Corporate Buyers

For technology firms, automotive OEMs, industrial automation, and any business with material chip dependency, three planning principles separate effective procurement strategy from posture:

  1. Dual-source by region, not just by vendor. Single-region exposure — even to vendors with multi-region capacity — has been re-priced as material strategic risk. Mature-node Chinese supply may be commercially attractive, but its strategic acceptability is now a board-level question.
  2. Plan for the cost premium as a long-duration feature, not a transitional cost. Pricing models built on pre-2022 Taiwan economics under-state run-rate cost by a meaningful margin.
  3. Hedge against export-control evolution. The boundary between commercially permissible and policy-restricted chip categories has moved every 12–18 months since 2022 and shows no sign of stabilising. Sourcing strategies that depend on current rules being current in three years are over-confident.

Who Wins From Here

The cycle's winners are increasingly clear:

  • TSMC remains the structural winner — its multi-region capacity gives it pricing power in both the policy-protected and cost-competitive segments
  • Memory leaders (Samsung, SK Hynix, Micron) have benefited from synchronous demand and policy support; the structural over-capacity risk of past cycles is materially mitigated
  • Equipment makers — ASML in lithography, Applied Materials in deposition, Tokyo Electron in etch — capture rent from the multi-region buildout regardless of which fab operator deploys
  • Materials and specialty gas suppliers in stable jurisdictions are seeing structural margin expansion

The exposed positions:

  • Pure mature-node logic and memory players facing Chinese capacity-driven price compression
  • Single-region fab operators without diversified production geography
  • Downstream buyers with single-source dependencies who delayed procurement diversification through 2024–25

The industrial-policy cycle is not over. The 2026–2030 phase will be defined by execution rather than commitment — and by whether the policy frameworks that subsidised the capacity buildout sustain the demand-pull that keeps the new geography commercially viable.


The World Research Institute provides semiconductor supply-chain risk assessment, procurement diversification frameworks, and sector-specific exposure analysis. Contact our team to commission tailored research.

Share This Analysis